Novel high voltage LDMOS using a variable fermi-potential field plate for best switching FOM and reliability tradeoff

In this paper, we discuss the fundamental design tradeoff among specific on-resistance (R_{on, sp}), gate charge (C_gg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (R_{on, sp}*Q_gg) and a robust I_{d, lin} shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.