Title :
Versatile HV lateral JFETs design in a 0.18μm SOI superjunction BCD technology
Author :
Yang Hao ; Kuniss, Uta ; Kittler, Gabriel ; Hoelke, Alexander
Author_Institution :
X-FAB Sarawak Sdn. Bhd., Kuching, Malaysia
Abstract :
This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(threshold voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.
Keywords :
CMOS integrated circuits; bipolar integrated circuits; junction gate field effect transistors; power field effect transistors; semiconductor device breakdown; silicon-on-insulator; Idsat; N-ch JFET; P-ch JFET; SOI superjunction BCD technology; Si; scalable breakdown voltage capability; size 0.18 mum; variable threshold voltage; versatile HV lateral JFET design; Doping; Electric potential; JFETs; Junctions; Logic gates; MOS devices; Silicon;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4673-5134-8
DOI :
10.1109/ISPSD.2013.6694449
