• DocumentCode
    661594
  • Title

    A novel super-junction trench gate MOSFET fabricated using high aspect-ratio trench etching and boron lateral diffusion technologies

  • Author

    Kim, S.G. ; Park, H.S. ; Yoo, S.W. ; Na, K.I. ; Koo, J.G. ; Won, J.I. ; Park, K.S. ; Yang, Y.S. ; Lee, J.H.

  • Author_Institution
    Div. of Green Energy Eng., Uiduk Univ., Daejeon, South Korea
  • fYear
    2013
  • fDate
    26-30 May 2013
  • Firstpage
    233
  • Lastpage
    236
  • Abstract
    We propose a super-junction trench gate MOSFET (SJ TGMOSFET) which is fabricated with a simple p-pillar forming process using deep trench and boron silicate glass (BSG) doping process technologies to reduce the process complexity. The p-pillar region is formed through lateral boron diffusion from BSG film and annealing process after the silicon deep etching. For the SJ TGMOSFET fabricated with BSG lateral diffusion, the controls of the boron concentration and the profile are important to achieve the charge balance between p-and n-pillars. Throughout the various boron doping experiments as well as process simulation, we optimize process conditions related with p-pillar depth, BSG doping concentration and diffusion temperature. Due to the trenched p-pillar, the potential of the SJ TGMOSFET more uniformly distributes and widely spreads into the bulk region of the n-drift layer comparing to the conventional TGMOSFET. The measured breakdown voltage of SJ TGMOSFET increases at least 28% than that of the conventional TGMOSFET.
  • Keywords
    MOSFET; annealing; boron compounds; etching; glass; junction gate field effect transistors; semiconductor doping; silicon compounds; BSG; SJ TGMOSFET; annealing process; boron lateral diffusion technology; boron silicate glass doping process technology; breakdown voltage; charge balance; high aspect-ratio trench etching; n-drift layer region; n-pillar; silicon deep etching; simple p-pillar forming process; super-junction trench gate MOSFET fabrication; Annealing; Boron; Doping; Etching; Films; Logic gates; MOSFET;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
  • Conference_Location
    Kanazawa
  • ISSN
    1943-653X
  • Print_ISBN
    978-1-4673-5134-8
  • Type

    conf

  • DOI
    10.1109/ISPSD.2013.6694459
  • Filename
    6694459