DocumentCode :
661599
Title :
Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI
Author :
Abou-Khalil, Michel J. ; Letavic, Theodore J. ; Slinkman, James A. ; Joseph, Alvin J. ; Botula, Alan B. ; Jaffe, Mark D.
Author_Institution :
Device & Technol. Dev., IBM Microelectron., Essex-Junction, VT, USA
fYear :
2013
fDate :
26-30 May 2013
Firstpage :
253
Lastpage :
255
Abstract :
We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.
Keywords :
CMOS integrated circuits; MOSFET; ionisation; semiconductor device breakdown; semiconductor thin films; silicon-on-insulator; 3D TCAD simulations; LDMOS structure; RESURF principal; RX field plate shapes; RX-bound field plates; angular RX field plates; baseline CMOS SOI process; body-contacted n-channel LDMOS devices; device scaling; drift region; floating body; high breakdown voltage; impact ionization rate; lateral electric field coupling; lateral tapered active field-plate LDMOS device; size 180 nm; thin body SOI technology; thin-film SOI; uniform longitudinal drift region electric field; voltage 20 V; CMOS integrated circuits; Couplings; Electric breakdown; Electric potential; Impact ionization; Logic gates; Solid modeling; 20V CMOS in SOI; High Breakdown SOI devices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
ISSN :
1943-653X
Print_ISBN :
978-1-4673-5134-8
Type :
conf
DOI :
10.1109/ISPSD.2013.6694464
Filename :
6694464
Link To Document :
بازگشت