A new type of SiC-VJFET with extreme low feedback capacitance

In this paper, we propose a novel SiC vertical JFET (VJFET) with low feedback capacitance C_rss by using a device simulator. A key feature of the proposed VJFET is the p⁺ screen grid inserted between gate and drain electrode. The screen grid is effective to reduce the C_rss by 80% compared to conventional VJFETs. Due to the low C_rss, total power loss of the proposed VJFET is the lowest among existing SiC power devices. This new VJFET can be a promising candidate for a high-speed and low-loss SiC power device.