A performance evaluation of a probabilistic parallel genetic algorithm: FPGA vs. multi-core processor

Author

Jewajinda, Yutana

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

298

Lastpage

301

Abstract

This paper presents a performance evaluation between hardware and software implementation of a probabilistic parallel genetic algorithm. The compact genetic algorithm is extended to support parallel implementation. The parallelized compact genetic algorithm is implemented in FPGA hardware and parallelized software version running on multicore processors for performance evaluation using standard benchmark functions. The experimental results show that the hardware implementation of the parallel compact genetic algorithm delivers speedup of between 100-fold to 500-fold depending on problems size and number of generations.

Keywords

field programmable gate arrays; genetic algorithms; mathematics computing; multiprocessing systems; parallel algorithms; performance evaluation; probability; FPGA hardware; generation number; hardware implementation; multicore processor; parallelized compact genetic algorithm; parallelized software implementation; performance evaluation; probabilistic parallel genetic algorithm; problem size; standard benchmark functions; Computer science; Conferences; Decision support systems; Handheld computers; FPGA; Multi-core processor; Parallel genetic algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Engineering Conference (ICSEC), 2013 International

Conference_Location

Nakorn Pathom

Print_ISBN

978-1-4673-5322-9

Type

conf

DOI

10.1109/ICSEC.2013.6694797

Filename

6694797