DocumentCode
661974
Title
A design technique for a high-speed SAR ADC using non-binary search algorithm and redundancy
Author
Okazaki, Tadatsugi ; Kanemoto, Daisuke ; Pokharel, R. ; Yoshida, Kenta ; Kanaya, Haruichi
Author_Institution
Grad. Sch. of ISEE, Kyushu Univ., Fukuoka, Japan
fYear
2013
fDate
5-8 Nov. 2013
Firstpage
506
Lastpage
508
Abstract
This paper presents a design technique of minimizing time for each bit decision and adding appropriate redundancy bits. The technique helps the design of a SAR ADC. We show that the conversion time of proposed SAR ADCs can get faster than that of conventional ones by using the technique.
Keywords
analogue-digital conversion; redundancy; search problems; bit decision; conversion time; high-speed SAR ADC; nonbinary search algorithm; redundancy bits; Algorithm design and analysis; Conference proceedings; Design methodology; Educational institutions; Microwave circuits; Redundancy; Algorithms; binary codes; design methodology; optimization; redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference Proceedings (APMC), 2013 Asia-Pacific
Conference_Location
Seoul
Type
conf
DOI
10.1109/APMC.2013.6694846
Filename
6694846
Link To Document