Chip design of 5.2 GHz frequency synthesizer with a gate-to-source feedback Colpitts VCO

A 5.2 GHz phase-locked loop (PLL) frequency synthesizer is implemented in TSMC 0.18 um CMOS process. The main features include the uses of a gate-to-source feedback Colpitts voltage-controlled oscillator (VCO) to lower phase noise, and an off-chip tunable low-pass filter to compensate the variations of resistance R and capacitance C to speed locking time and reduce chip area. At the supply voltage of 1.8-V, measured results achieve the tunable locked output frequency from 4.97~5.32 GHz, corresponding to 6.8% and at 1 MHz offset frequency away from the center frequency of 5.2 GHz, the phase noise of -109.57 dBc/Hz and the output power of -11.35 dBm with a reference spur of -58 dBc respectively. The overall power consumption is 22.4 mW. Including pads, the chip area is 0.7654 (0.89×0.86) mm².