A dual-mode RF CMOS power amplifier with nonlinear capacitance compensation

Author

Seunghoon Kang ; Bonhoon Koo ; Songcheol Hong

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

fYear

2013

fDate

5-8 Nov. 2013

Firstpage

778

Lastpage

780

Abstract

A fully integrated dual-mode CMOS power amplifier (PA) with nonlinear MOS capacitance compensation is presented using 0.18-μm RF CMOS process. The proposed technique is used to implement dual mode structure as well as reduces AM-PM distortion. Dual-mode output matching network using transmission line transformer (TLT) is implemented for efficient dual mode operation. With a supply voltage 3.5V, the PA has the power gain of 26.2 and 14.2dB in low power mode (LPM) and high power mode (HPM), respectively. The quiescent current is only 28mA at LPM. The maximum linear output power satisfying 3GPP WCDMA modulated signal is 28/16.3dBm with a PAE 33.8/10.2% in the HPM/LPM.

Keywords

CMOS integrated circuits; capacitance; compensation; radiofrequency power amplifiers; transformers; transmission lines; 3GPP WCDMA modulated signal; AM-PM distortion; HPM; LPM; RF CMOS process; TLT; current 28 mA; dual-mode CMOS power amplifier; dual-mode output matching network; efficiency 10.2 percent; efficiency 33.18 percent; gain 14.2 dB; gain 26.2 dB; high power mode; low power mode; nonlinear MOS capacitance compensation; size 0.18 mum; transmission line transformer; voltage 3.5 V; CMOS integrated circuits; Capacitance; Linearity; Logic gates; MOS devices; Power amplifiers; Radio frequency; CMOS; Capacitance compensation; WCDMA; dual-mode; power amplifier (PA);

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2013 Asia-Pacific

Conference_Location

Seoul

Type

conf

DOI

10.1109/APMC.2013.6694929

Filename

6694929