DocumentCode :
662295
Title :
Design methodology of tunable impedance matching circuit with SOI CMOS tunable capacitor array for RF FEM
Author :
Bum-Kyum Kim ; Taeyeop Lee ; Donggu Im ; Do-Kyung Im ; Bonkee Kim ; Kwyro Lee
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2013
fDate :
5-8 Nov. 2013
Firstpage :
7
Lastpage :
9
Abstract :
For the tunable RF FEMs or Antennas, analysis on optimal design of tunable capacitors which consist of MIM capacitors and RF CMOS switches is performed in terms of quality factor, tuning ratio and harmonics. To handle up to +36dBm RF signal, the Stacked-FET and series Capacitor-Transistor-Capacitor (CTC) configuration applied Coupled-Bias(CB) are proposed, which in addition to being high-linearity can eliminate a negative voltage generator. Using the designed tunable capacitors, optimal tunable matching circuit is proposed.
Keywords :
CMOS integrated circuits; MIM devices; Q-factor; antenna arrays; broadband antennas; capacitors; circuit tuning; harmonics; impedance matching; integrated circuit design; silicon-on-insulator; MIM capacitors; RF CMOS switches; SOI CMOS tunable capacitor array; design methodology; harmonics; quality factor; series capacitor-transistor-capacitor configuration applied coupled-bias; stacked-FET; tunable RF FEMs; tunable RF antennas; tunable capacitors; tunable impedance matching circuit; tuning ratio; Antenna measurements; Arrays; Capacitors; Harmonic analysis; Radio frequency; Transistors; Tuning; SOI; Tunable capacitor; cellular antennas; impedance matching; stacked FET; variable capacitor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Conference Proceedings (APMC), 2013 Asia-Pacific
Conference_Location :
Seoul
Type :
conf
DOI :
10.1109/APMC.2013.6695173
Filename :
6695173
Link To Document :
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