Behavioral modeling of outphasing amplifiers considering memory effects

This paper proposes a behavioral model structure for outphasing amplifiers. The model performance is evaluated on a class-D CMOS outphasing amplifier and compared with two models found in the literature. The proposed model structure also allows the use of memory in a parallel Hammerstein-like setting. The proposed models show improvements in adjacent channel error power ratio (ACEPR) of approximately 5 dB in addition to being linear in the parameters. The lower model errors enable the use and design of improved predistorters taking frequency dependency (memory effects) in outphasing amplifiers into account.