Title :
Design of instruction decode logic for dual-issue superscalar processor based on LEON2
Author :
Xue Yang ; Lixin Yu ; Wei Zhuang ; Yingpan Wu ; Li Hao
Author_Institution :
Dept. SoC, Beijing Microelectron. Tech. Instn. (BMTI), Beijing, China
Abstract :
An instruction decode logic available for dual-issue pipeline processor is presented in this paper. The structure is based on the LEON2 scalar processor since it is a multifunctional processor widely used in many application scenarios. Focusing on the decode part, mainly three problems are solved. A comparator that can help to get the right nPC (nest program counter) is introduced for instruction dispatching. Dependences between two instructions in parallel are settled by the added Branch detector, and operands hand over to each other between the two pipelines are implemented by brought in forwarding roads. Structure block diagrams of the dual-issue pipeline and the new function units added are given. Run testing program Dhrystone on the two different structures, results indicate that the performance of the dual-issue structure is improved by 30.18% comparing to the single-issue structure.
Keywords :
comparators (circuits); counting circuits; instruction sets; logic design; microprocessor chips; parallel architectures; pipeline processing; program testing; Dhrystone; LEON2 scalar processor; added branch detector; comparator; dual issue pipeline processor; dual issue superscalar processor; instruction decode logic design; instruction dispatching; multifunctional processor; next program counter; operands hand over; right nPC; run testing program; structure block diagram; dual-issue pipeline; instruction decoding; instruction dependences; instruction dispatching;
Conference_Titel :
Consumer Electronics ?? Berlin (ICCE-Berlin), 2013. ICCEBerlin 2013. IEEE Third International Conference on
Conference_Location :
Berlin
Print_ISBN :
978-1-4799-1411-1
DOI :
10.1109/ICCE-Berlin.2013.6697986