DocumentCode
664862
Title
A low energy HEVC Inverse DCT hardware
Author
Kalali, Ercan ; Ozcan, Erdem ; Yalcinkaya, Ozgun ; Hamzaoglu, Ilker
Author_Institution
Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey
fYear
2013
fDate
9-11 Sept. 2013
Firstpage
123
Lastpage
124
Abstract
In this paper, a novel energy reduction technique for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) for all Transform Unit (TU) sizes is proposed. An efficient HEVC 2D IDCT hardware for all TU sizes is also designed and implemented using Verilog HDL. The proposed hardware can decode 48 Quad HD (3840×2160) video frames per second. The proposed technique reduced its energy consumption up to 23%.
Keywords
discrete cosine transforms; hardware description languages; inverse transforms; video codecs; video coding; 2D IDCT hardware; TU size; Verilog HDL; energy consumption; energy reduction technique; high efficiency video coding; inverse DCT hardware; inverse discrete cosine transform; low energy HEVC; transform unit size; Discrete cosine transforms; Energy consumption; Field programmable gate arrays; Hardware; Hardware design languages; Standards; Video coding; Energy Reduction; HEVC; Hardware; IDCT;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics ?? Berlin (ICCE-Berlin), 2013. ICCEBerlin 2013. IEEE Third International Conference on
Conference_Location
Berlin
Print_ISBN
978-1-4799-1411-1
Type
conf
DOI
10.1109/ICCE-Berlin.2013.6698021
Filename
6698021
Link To Document