• DocumentCode
    66527
  • Title

    Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

  • Author

    Byeong-Woon Hwang ; Ji-Woon Yang ; Seok-Hee Lee

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • Volume
    62
  • Issue
    1
  • fYear
    2015
  • fDate
    Jan. 2015
  • Firstpage
    171
  • Lastpage
    177
  • Abstract
    An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.
  • Keywords
    MOSFET; semiconductor device models; 2D technology computer-aided design simulation; MOSFET; accumulation operation mode; device structures; drain current; electric fields; explicit analytical current-voltage model; full depletion operation mode; long-channel double-gate junctionless transistors; mobile charges; partial depletion operation mode; threshold voltage model; Analytical models; Computational modeling; Electric potential; Logic gates; Mathematical model; Numerical models; Transistors; Compact modeling; junctionless (JL) transistor; multigate MOSFET; variability; variability.;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2014.2371075
  • Filename
    6971183