Study of influential parameters for lead-free flip chip solder joint cracking

In this work, we investigated the flip chip lead-free solder joint cracking phenomenon. A study on the occurrence and severity of solder joint cracking before the encapsulation operation across several device technologies enabled the identification of the dominant parameters. The respective influence of CJ reflow profile, solder joint density in chip corners, substrate core thickness and the solder voiding are discussed with respect to this phenomenon. The CJ reflow profile was found to be the most significant parameter in this study. The influence of the CJ reflow profile is described with respect to measured chip warpage reduction and frequency of solder joint cracking. Amongst the more secondary relationships, a comparison between various solder joint densities in chip corners revealed that higher solder joint density exhibits an improved resistance to crack occurrence and propagation. In terms of substrate core thickness, coreless packages have shown to be more sensitive than packages with cored substrates to mechanical stresses and vibrations that can induce cracking. Finally, the presence of voids in solder was found to be an aggravating parameter based predominantly on its effect on cracking severity. These relationships are discussed in detail along with hypotheses to support same.