STMicroelectronics package design rules Check coverage enhancement with Cadence Ravel

Today, new technologies in packaging assembly method (e.g. Copper Pillar FC bumping, 3D, etc...) are generating many new design rules. Historically the Wire Bond assembly was largely used and mastered but due to new technological breakthrough in the Flip Chip assembly method (eg Copper Pillar bumping) the trend is reversed and most of ST projects are now developed with Flip Chip. In the previous Minapad 2012 paper we presented a status on several design rules checkers [STMicroelectronics assembly and substrate Design Rule Check: state of the art - MINAPAD 2012]. The result were that Wire Bond is well covered thanks to an internal tool (ICPack) while Flip Chip technology was not presenting the same status: Existing checks included in design tools are limited to 10% of design rules coverage and is not covering the critical check to ensure a good manufacturing yield. In 2010, Cadence Design Systems presented a design rule verification system for the Cadence Allegro platform based on a new language called Ravel, standing for “Relational Algebra Verification Expression Language” utilizing the concepts of relational algebra. The Constraint Manager integrates compiled RAVEL rules to display standard design rule violation flags directly in the design tool, making the use of RAVEL transparent for the user. In this paper we will show the benefits ST took from this new capability by extending the Design Rule Check coverage mainly focusing on the Flip Chip technology. Ravel has been used to check the authorized bump matrix configurations, enabling faster design and safer assembly solution.