Demonstration of a 3D embedded wafer-level SIP for smartcard application

Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture. Individual strata of 100 μm are fabricated using the same principle than standard eWLB wafers. Specific thin wafer handling and temporary wafer-level-bonding technologies have been also developed to stack the strata one on each other involving a carrier flip-flop technique involving very tight thermal window processes. Redistribution layer consisting of polymers passivation and copper lines is formed on top of each individual stratum. Strata stacking is performed by permanent bonding polymer coating. Vertical interconnections are realized by means of through polymer via (TPV) technologies introduced at the third levels. Wafer level bumping is finally formed to assemble the dies on the frame by flip chip. A dedicated test vehicle has been designed with different combinations of daisy chains including chip metallization, fan out RDL and TPV allowing setup each brick of process and finally achieving the complete integration. A full functional demonstrator comprising two levels of memory dies on the bottom strata and one level of micro-controller dies on the top stratum has been finally fabricated and tested using this integration.