DocumentCode
665352
Title
Challenges in IC-package-PCB co-design of an advanced flip-chip PoP package for a mobile application
Author
Lecoq, Xavier ; Cosmo, Stephane ; Bacle, Prem ; Devey, Corinne ; Bayet, Olivier ; Schwarz, Lawrence
Author_Institution
STMicroelectron. Grenoble, Grenoble, France
fYear
2013
fDate
9-12 Sept. 2013
Firstpage
1
Lastpage
5
Abstract
When it comes to developing an advanced flip-chip Package-on-Package (PoP) for a mobile application, challenges are daunting: what are the keys to insure that the IC-package-PCB system is optimized with respect to the physical, the electrical and the thermal constraints while meeting the cost, the technology, the integration and the low power targets? The combined physical and electrical system co-design process enables us to reach high-performance and quality results. From the early prototyping stage to the final implementation, the physical co-design must follow electrical design rules, as well as constraints coming from substrate technology, manufacturing and assembly. As the electrical rules are application, frequency and technology dependent, early electro-magnetic (EM) and electrical simulations are always required to define the first guidelines, including floorplan and routing recommendations on the IC, package and PCB. Even if the flow can be either PCB-driven or IC-driven, the target should always be the global optimization from a system and customer point of view. As the level of integration is always very high, it is essential to have quickly a global view on the sensibility of high-speed interfaces and demanding IP´s. Then the next steps are to obtain sufficient design margin and to properly balance the routing resources. Based on the implementation of a digital baseband, this paper shows the important aspects of the IC-package-PCB co-design process, highlights the value of early Electro-Magnetic (EM) and electrical simulations (including Power Integrity / Signal Integrity [PI/SI]), and illustrates the links between the system co-design and substrate technology / assembly / manufacturing constraints.
Keywords
electromagnetic waves; flip-chip devices; integrated circuit packaging; printed circuit design; IC-package-PCB codesign; advanced flip-chip PoP package; electrical constraints; electrical simulations; electromagnetic simulations; flip-chip package-on-package; mobile application; substrate technology; thermal constraints; Assembly; Mobile communication; Routing; Silicon; System-on-chip; Web sites; assembly; manufacturing simulations; physical / electrical IC-package-PCB co-design; power and signal integrity; thermal;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics Packaging Conference (EMPC) , 2013 European
Conference_Location
Grenoble
Type
conf
Filename
6698675
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