Bow management with temperature for thin chips integration

3D integration and TSV process require chip thinning. For TSV mid process or TSV last, chips with silicon thicknesses below 200μm or even below 100μm are becoming more and more usual. Due to this silicon thickness decrease, those chips are very sensitive to the deposit layers stress. A precise chip bow management with temperature is so mandatory for these thin chips mounting compatibility. The first part of the paper will discuss on basic bow analysis with silicon thickness and dielectric or organic material, as passivation polymer layers, at room temperature. Moreover, a dielectric deposit process development study on 300mm wafers will be presented to manage layer stress at room temperature. The second part of the paper will deal with bow variation with a range of temperature from room temperature to reflow process maximum temperature. In-house measured material properties will be detailed. This will include measurement results for Young modulus, and layer stresses. Finally, simple model and simulation first results will be presented and compare with thermal deformation measurement at chip level.