Title :
Comparative of HLS and HDL implementations of a grid synchronization algorithm
Author :
Sanchez, F.M. ; Mateos, Raul ; Bueno, Emilio J. ; Mingo, J. ; Sanz, I.
Author_Institution :
Dept. de Electron., Univ. de Alcala, Alcala de Henares, Spain
Abstract :
Control in power electronics develop new algorithms that increase computational complexity and sampling frequency. This fact means that traditional software implementations on DSPs does not satisfy the control constrains anymore moving those implementation to FPGAs, what everyone knows that is not a trivial task. This paper will show that HLS tools such Vivado HLS are mature enough to start considering it the first approach to the required hardware implementation of the proposed algorithm. For a comparative purpose, a grid synchronization algorithm developed in HDL previously has been redesigned using the HLS tools.
Keywords :
field programmable gate arrays; high level synthesis; power grids; synchronisation; DSP; FPGA; HDL implementation; HLS tool; Vivado HLS; computational complexity; grid synchronization algorithm; high level synthesis; sampling frequency; Computer architecture; Field programmable gate arrays; Hardware; Hardware design languages; Phase locked loops; Software; Synchronization; FPGAs; Grid Synchronization; High Level Synthesis; Power Electronics;
Conference_Titel :
Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE
Conference_Location :
Vienna
DOI :
10.1109/IECON.2013.6699478
