Memory requirements analysis for PRP and HSR hardware implementations on FPGAs

Author

Araujo, Jose Angel ; Lazaro, J. ; Astarloa, Armando ; Moreira, Naiara ; Garcia, Alvaro

Author_Institution

Dept. of Electron. Technol., Univ. of the Basque Country UPV/EHU, Bilbao, Spain

fYear

2013

fDate

10-13 Nov. 2013

Firstpage

2297

Lastpage

2302

Abstract

The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated information. In this paper the requirements of memory needed for a hardware implementation are analyzed.

Keywords

field programmable gate arrays; local area networks; protocols; storage management chips; FPGA; HSR hardware implementations; IEC62439-3; PRP hardware implementations; high availability automation network; high-availability seamless redundancy; memory requirements analysis; parallel redundancy protocol; Computer aided manufacturing; Delays; Field programmable gate arrays; Memory management; Random access memory; Redundancy; Standards; Ethernet; HSR; IEC62439-3; PRP; availability; redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE

Conference_Location

Vienna

ISSN

1553-572X

Type

conf

DOI

10.1109/IECON.2013.6699489

Filename

6699489