Title :
Efficient non-iterative fixed-period SVM training architecture for FPGAs
Author :
Phear, Peter Bernard Ashleigh ; Rajkumar, R.K. ; Isa, Dino
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Nottingham, Kuala Lumpur, Malaysia
Abstract :
A method for efficient non-iterative fixed-period SVM training is presented. A highly pipelined, parallel, and concurrent systolic processing-based hardware architecture overview for FPGA implementation is also provided. The architecture´s training performance is simulated in software and tested successfully by solving two classification problems utilising a 2-dimensional linearly-separable dataset and a 2-dimensional XOR-problem dataset. In both cases the trained optimal SVM function-model classified both datasets with 100% accuracy and thus verified the training architecture´s feasibility and potential for further investigation and FPGA implementation.
Keywords :
electronic engineering computing; field programmable gate arrays; support vector machines; systolic arrays; 2-dimensional XOR-problem dataset; FPGA; concurrent systolic processing-based hardware architecture; noniterative fixed-period SVM training architecture; parallel systolic processing-based hardware architecture; pipelined systolic processing-based hardware architecture; Computer architecture; Hardware; Linear programming; Optimization; Support vector machines; Training; Vectors;
Conference_Titel :
Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE
Conference_Location :
Vienna
DOI :
10.1109/IECON.2013.6699508