Interpolation by a prime factor other than 2 in low-voltage low-power ΣΔ DAC

This paper presents power optimization of a sigma-delta (ΣΔ) modulator based digital-to-analog converter (DAC) for hearing-aid audio back-end application. In a number of state-of-the-art publications the oversampling ratio (OSR) of the ΣΔ modulator is chosen as a factor of integer power of two. The reason given is the simplicity of the interpolation filter (IF) block. However, being able to choose OSR factors of integer powers of two only, might be restricting and not necessarily optimal. Therefore the ΣΔ modulator based DAC designs with multistage IF that include a stage performing oversampling by a factor of 3 are investigated. This new design freedom is used to lower the operating frequency of the whole DAC and save considerable amount of power. It is shown that the figure-of-merit (FOM) of such designs can be lower than designs using oversampling by a factor of integer powers of two. The same optimization approach can be used for other low voltage low power portable audio applications (mobile phones, notebook computers etc.).