SRT radix-2 dividers with (5,4) redundant representation of partial remainder

A wide range of digit recurrence division algorithms take advantage of the redundant representation (such as carry-save) of the partial remainder. This allows performing carry free addition, which leads to higher performance. This paper introduces a new type of redundant representation of partial remainder for radix-2 SRT dividers, which uses 5 bits of representation for each 4 bits of the remainder. Compared to the classic carry-save representation (which uses 2 bits of representation for each bit of the remainder), the proposed approach uses a smaller number of flip-flops to store partial remainders. We investigate the cost-area trade-offs in our approach in several FPGA implementations.