Single poly non-volatile memory cells for miniaturized sensors in 90nm CMOS technology

We present the evaluation of three different single poly non-volatile memory (NVM) cells (flash-/floating gate memory) for the use in a micro-implant application, all implemented in the very same 90nm CMOS technology. Two of them have been adapted from previous publications while a third structure is novel. The evaluation criteria are given by the target application, a sensory micro-implant that is powered by and communicates with a standard NFC reader as a type 1 NFC tag. This gives us in particular specific timing restrictions for unbuffered read and write operations and a (somewhat less specific) power restriction, since it needs to be realistically supplied by power harvesting from the NFC reader. We conclude with suggesting a cell that offers a good trade-off between a write speed of below 2.5ms and achieving tunneling using voltages of +/-4.5V. The later we postulate is a good indicator of the power consumption imposed on the micro-implant system, as the losses in the charge pump that provides this high voltages are monotonically increasing with this voltage and will be much more significant than the tunneling current itself.