Interpolating time counter with multi-edge coding

This paper presents the design, operation and test results of an interpolating time counter with a multi-edge coding principle implemented in the second stage of interpolation. The counter is implemented in an FPGA device (Spartan-6, Xilinx) and provides a 2.7 ps resolution, 8 ps precision and 1 s measurement range. The development of such a high performance instrument needs to solve several design problems. The main of them are an implementation of a pattern generator and elimination of bubble errors. We designed and tested two pattern generators based respectively on look-up tables and fast carry chains. The former one is simpler for implementation while the latter allows to control parameters of the pattern signal. This control feature is especially important for the quality of T/D conversion that depends, among others, on the complexity of the pattern signal. We tested three variants of TDC based in turn on coding of three rising, three falling or six alternated edges.