DocumentCode :
667957
Title :
High density and reliable packaging technology with Non Conductive Film for 3D/TSV
Author :
Mori, Kazuo ; Ono, Yuto ; Watanabe, Shigetaka ; Ishikawa, Takaaki ; Sugiyama, Masakazu ; Imasu, Satoshi ; Ochiai, Toshihiko ; Mori, Ryuhei ; Kida, T. ; Hashimoto, Toshikazu ; Tanaka, Hiroya ; Kimura, Mizue
Author_Institution :
Renesas Electron. Corp., Kawasaki, Japan
fYear :
2013
fDate :
2-4 Oct. 2013
Firstpage :
1
Lastpage :
7
Abstract :
The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermal-compression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.
Keywords :
DRAM chips; flip-chip devices; logic devices; microassembling; semiconductor device reliability; three-dimensional integrated circuits; 3D TSV; 3D integrations; DRAM; flip chip assembly process; high density packaging technology; high humidity test; high temperature storage test; logic device; logic die; memory die; nonconductive film; organic substrate; pressure cooker test; reliability test; reliable packaging technology; size 28 nm; size 40 mum; size 50 mum; temperature cycling test; thermal compression bonding method; time 1000 h; time 300 h; time 500 h; unbiased highly accelerated stress test; underfill material; Bonding; Flip-chip devices; Microassembly; Reliability; Substrates; Three-dimensional displays; Through-silicon vias; 3D integration; Non Conductive Film (NCF); Thermal-compression bonding; Through Silicon Via (TSV);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1109/3DIC.2013.6702322
Filename :
6702322
Link To Document :
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