• DocumentCode
    667959
  • Title

    A 3D Process Design Kit generator based on customizable 3D layout design environment

  • Author

    Cibrario, G. ; Henry, David ; Chantre, C. ; Cuchet, Robert ; Berthelot, Audrey ; Azizi-Mourier, Karim ; Gary, Marjorie ; Gays, Fabien

  • Author_Institution
    LETI, CEA, Grenoble, France
  • fYear
    2013
  • fDate
    2-4 Oct. 2013
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    3D integration provides different technological approaches as new opportunities for design and architecture alternatives. Circuit integration can now be achieved by using various interconnection concepts such as Through Silicon Vias (TSV last), ReDistribution Layer (RDL), pillars, bumps and micro-bumps. The key challenge from the design kit point of view is now to make all these concepts accessible and easy to use for 3D IC design benchmarking, leading to a generic 3D platform offering various interconnection options for the end-user with on-demand customization of the 3D layout environment. The first section of this paper will give an overview of the LETI 3D technological offer through the Open 3D™ platform and present the context in terms of Process Design Kit (PDK) development. Second section will describe the approach and the proposed solution through a configurable PDK, a PDK generator software and the associated user-friendly interface. Finally, last section will focus on the 3D layout environment and methodology used to design a 3D demonstrator with some examples.
  • Keywords
    circuit CAD; integrated circuit interconnections; integrated circuit layout; 3D IC design benchmarking; 3D process design kit generator; LETI 3D technology; Open 3D platform; circuit integration; customizable 3D layout design; generic 3D platform; interconnection option; process design kit development; Design automation; Generators; Integrated circuit interconnections; Layout; Software; Three-dimensional displays; Through-silicon vias; 3D Layout Environment; 3D interconnection modules; Design Kit; Design rules; Parameterized Cells (Pcells); Through Silicon Vias (TSV);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1109/3DIC.2013.6702324
  • Filename
    6702324