Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory

The Young´s modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Young´s modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Young´s modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness was bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreased chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in 20-μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects a minority carrier generation lifetime, consequently shortening the retention time of DRAM cell.