3D memory chip stacking by multi-layer self-assembly technology

Author

Fukushima, Tetsuya ; Bea, Jichel ; Murugesan, Mariappan ; Son, H.-Y. ; Suh, M.-S. ; Byun, K.-Y. ; Kim, Nam-Soo ; Lee, Ki-Won ; Koyanagi, Mitsumasa

Author_Institution

New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan

fYear

2013

fDate

2-4 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg μbump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, μbump shapes, and μbump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-μbump daisy chains in the stacked memory chips.

Keywords

copper; integrated circuit layout; integrated circuit metallisation; integrated memory circuits; microassembling; photolithography; self-assembly; silver alloys; stacking; surface tension; three-dimensional integrated circuits; tin alloys; wetting; 3D memory chip stacking; Cu-SnAg; TSV technology; chip-substrate surface; electrical joining; microbump layout; microbump shape; multilayer self-assembly technology; surface tension driven self-assembly technique; thermal compression; wetting property; Accuracy; Assembly; Bonding; Self-assembly; Stacking; Substrates; Three-dimensional displays; 3D Chip Stack; Memory; Microbump; Self-Assembly; TSV;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2013 IEEE International

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1109/3DIC.2013.6702360

Filename

6702360