Title :
Contact testing of copper micro-pillars with very low damage for 3D IC assembly
Author :
Yaglioglu, Onnik ; Eldridge, Ben
Author_Institution :
FormFactor Inc., Livermore, CA, USA
Abstract :
3D IC integration offers a new paradigm of system assembly, which enables further miniaturization and new architectures driven mostly by the next generation mobile electronics applications which require larger bandwidth, lower power consumption, smaller footprints and reduced cost. However, 3D integration presents test challenges and demands new test techniques. For the economic assembly of 3D stacks, high yield for each die needs to be assured before stacking. Even though the die are tested at wafer level with existing standard test techniques, during the wafer thinning, TSV formation and dicing, new defects may be introduced and these defects need to be caught before system assembly in order to achieve high yield. We present a highly scalable contactor solution, FormFactor NanopierceTM, which can be used in both probe card configuration(wafer level test), or socket configuration (die level test) which enables testing individual bare die for a known good die (KGD) solution, and similarly, testing a subassembly of dies for a known good stack (KGS) solution before final system assembly. One of the concerns of direct testing of microbumps is the potential damage on the microbumps that may be caused during testing, which can compromise subsequent assembly steps. We demonstrate full area direct contact tests results on Copper micropillars at 40μmx50μm wide I/O pattern consisting of 1104 micropillars and demonstrate very low damage on Cu micropillars. This is enabled by the fact that NanopierceTM contactor relies on many small contact points within one contact pad and good electrical connection can be achieved at low contact forces with minimal surface damage. Contact force per spring is 0.5g at 15μm overtravel.
Keywords :
copper; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; three-dimensional integrated circuits; 3D integrated circuit assembly; 3D integration; 3D stacks; FormFactor NanopierceTM; KGD; KGS; TSV formation; contact testing; copper micropillars; die level test; economic assembly; known good die solution; known good stack solution; microbump testing; probe card configuration; size 40 mum; size 50 mum; socket configuration; surface damage; system assembly; through silicon via; wafer level test; wafer thinning; Assembly; Conferences; Contacts; Sockets; Testing; Three-dimensional displays; Through-silicon vias; 3D Test; Copper Pillar; KGD; MicroBump; Nano; Socket; TSV;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
DOI :
10.1109/3DIC.2013.6702361