Title :
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC
Author :
Neela, Gopi ; Draper, J.
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Sustaining the trend of integration and energy efficiency, while remaining cost-effective, in the era of slower transistor scaling requires a new solution. Perhaps 3-dimensional integrated circuits (3DIC) are the best current solution to the physical limitations concerning interconnects. Among possible logic-on-logic 3DIC structures, face-to-face (F2F) bonded 3DICs provide the highest density interconnect between bonding tiers potentially without affecting the active layer density. In a F2F 3DIC the adjacent tiers are interconnected by bonding the top metal layer bondpoints. Similar to I/O, inter-tier signals assigned to bondpoints have an effect on standard cell placement. This assignment is critical for an efficient 3DIC layout. Unlike I/O signals, these inter-tier signals are very large in number making manual assignment (like I/O signals to pins) an extremely difficult task and calls for automated techniques. This paper introduces four new techniques: three variants of a nearest-neighbor approach and a midpoint based assignment. In all the techniques first the locations of cells that source or sink the inter-tier signals are estimated. Using the cells and the available bondpoints locations, the assignment is executed. These automated techniques achieved up to 10% less total net length and average net length when compared to a manual assignment. These techniques have potential to yield even better performance for large designs where a manual assignment would be impractical.
Keywords :
integrated circuit interconnections; integrated circuit layout; three-dimensional integrated circuits; 3-dimensional integrated circuits; 3D IC layout; F2F bonded 3D ICs; I/O signals; active layer density; automated techniques; cell placement; energy efficiency; face-to-face bonded 3D IC; integrated circuit interconnections; inter-tier signal assignment techniques; logic-on-logic 3D IC structures; midpoint based assignment; nearest-neighbor approach; top metal layer bondpoints; transistor scaling; Bonding; Computer architecture; Layout; Manuals; Microprocessors; Pins; Standards;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
DOI :
10.1109/3DIC.2013.6702384