Title :
Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC
Author :
Rajendran, Bipin ; Henning, A.K. ; Cronquist, B. ; Or-Bach, Zvi
Author_Institution :
Dept. of Electr. Eng., IIT Bombay, Mumbai, India
Abstract :
Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.
Keywords :
laser beam annealing; three-dimensional integrated circuits; classical dimensional scaling; fully depleted transistor channels; layout limitations; lithography costs; monolithic 3D IC; on-chip interconnect; pulsed laser annealing; time delays; Annealing; Integrated circuit modeling; Logic gates; Silicon; Three-dimensional displays; Transistors; 3D integration; SOI; laser annealing; simulation;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
DOI :
10.1109/3DIC.2013.6702386
