Optimal stacking of SOCs in a 3D-SIC for post-bond testing

Author

Pradhan, Manjari ; Giri, Chandan ; Rahaman, Hafizur ; Das, Debesh K.

Author_Institution

Dept. of Comput. Sci., Jadavpur Univ., Jadavpur, India

fYear

2013

fDate

2-4 Oct. 2013

Firstpage

1

Lastpage

5

Abstract

3D IC testing is one of the major concern in the semiconductor industry today. Multiple subsequent testing of partial stack during 3D assembly is required due to the die stacking steps of thinning, alignment and bonding. In this paper we address the problem of minimizing the total time of partial stack and complete stack testing. We analyze how the stacking sequence of different System-on-Chips (SOCs) in a 3D Stacked Integrated Circuit (SIC) affects the total test time. We propose an algorithm to find this stacking sequence to achieve the minimum test time. Our algorithm is run on ITC´02 benchmarks and the results are shown.

Keywords

integrated circuit bonding; integrated circuit testing; system-on-chip; three-dimensional integrated circuits; 3D IC testing; 3D SIC; 3D assembly; 3D stacked integrated sircuit; SOC; complete stack testing; die stacking steps; partial stack testing; postbond testing; semiconductor industry; stacking sequence; system-on-chips; Schedules; Silicon carbide; Stacking; System-on-chip; Testing; Three-dimensional displays; Three-dimensional integration; system-on-a-chip (SOC); test access mechanism; through silicon via;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2013 IEEE International

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1109/3DIC.2013.6702393

Filename

6702393