• DocumentCode
    668096
  • Title

    SPLG: A Tuned Signal Processing Library for GPU Architectures

  • Author

    Lobeiras Blanco, Jacobo ; Amor, Margarita ; Doallo, Ramon

  • Author_Institution
    Comput. Archit. Group, Univ. of A Coruna, A Coruna, Spain
  • fYear
    2013
  • fDate
    23-26 Oct. 2013
  • Firstpage
    184
  • Lastpage
    191
  • Abstract
    In order to increase the efficiency of existing software many works are incorporating GPU processing. However, despite the current advances in GPU languages and tools, taking advantage of their parallel architecture is still far more complex than programming standard multi-core CPUs. Performance profiling and analysis of known applications provides a useful insight of the hardware architecture and memory hierarchy. Afterwards, this analysis can be used to identify potential bottlenecks and tune other software so it can make a more efficient usage of the available resources. In this work we implement a small signal processing library which will be used to characterize the performance of most recent NVIDIA GPU architectures. The methodology used in our signal processing library is based on a series of building blocks that enable us to easily design several well-known algorithms with little effort. The library was built paying special attention to flexibility and adaptability. In this work we also show how a generic approach can be used to easily design these GPU algorithms while obtaining competitive performance, which results specially interesting from the productivity standpoint.
  • Keywords
    graphics processing units; parallel architectures; performance evaluation; signal processing; software libraries; CUDA; NVIDIA GPU architectures; SPLG; hardware architecture; memory hierarchy; parallel architecture; performance analysis; performance profiling; tuned signal processing library; Arrays; Graphics processing units; Instruction sets; Libraries; Registers; Transforms; CUDA; DCT; FFT; GPGPU; Hartley; Signal processing; tuned library;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th International Symposium on
  • Conference_Location
    Porto de Galinhas
  • Print_ISBN
    978-1-4799-2927-6
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2013.30
  • Filename
    6702596