High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n+-Doped Poly-Si NWs Channels Junctionless FETs

The gate-all-around sidewall-damascened sub10-nm in situ n⁺-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm² cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (VTii) and subthreshold swing (S.S.) on dimension of in situ n+-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. ~ 75 mV/decade; 2) low gate supply voltage (VG ) = 1.5 V; 3) high ON/OFF currents ratio (I_ON/I_OFF) ~ 8 × 10⁷ and significantly high-thermal stability without implantation processes and hydrogen-related plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications.