Accelerate high speed IO design closure with distributed chip IO interconnect model

This paper presents an overview of the applications of the distributed models representing chip IO power, ground and signal distribution systems from IO cells to die bumps. It provides a methodology of applying such models for on-die electrical performance assessment of IO power, ground and signal interconnects. It also demonstrates the die-to-die system-level IO SSO analysis with the chip interconnect model together with other models. The conventional chip interconnect model extraction tools are designed either for STA (static timing analysis) or for voltage drop analysis. In the former, the extraction tools mainly focus on RC (resistance and capacitance) extraction of signal traces but are neither keen to power rail network nor the couplings between power rails and signals. In the later, the tools extract the power rail network RC only by completely ignoring the signal parasitics. In both cases, the size of parasitic netlists including chip power and ground networks could be too large to be simulated. As a result, chip engineers have to guard their designs with a large amount of safety margin and leave the final signal integrity verification and fixes to the system engineers. On the other hand, the system engineers often have to either omit the chip IO interconnect model completely by connecting IO buffers with the package model directly or include a very simplified lumped on-chip power/ground model across all the driver power and ground terminals. Hence, the system-level SSO simulation results become either unduly pessimistic or over optimistic. A breakthrough extraction technology which generates a detailed model of chip IO power, ground and signal interconnects from bumps to IO circuits that fully represent the distributed nature of power, ground and signals as well as their electromagnetic coupling effects has been introduced by Cadence, which fills the gap between EDA tools and chip design needs for accurate on-die and system-level analysis of high-speed cha- nels and buses. The newly introduced chip IO interconnect model extraction takes chip layout data in GDSII or LEF/DEF formats, as well as the technology file for stackup process parameters and a user-specified configuration for net names, circuit definitions, etc. and then generates a comprehensive SPICE netlist that consists of a fully distributed IO power, ground and signal connections from IO cells to die bumps, including RDL and all the other metal layers, and bumps/ubumps. It accounts for all inductive and capacitive couplings between power, ground and signals on the chip. This extraction method offers both high spatial resolution and compact circuit size to ensure accuracy and efficiency. There is no practical limitation on the number of external nodes of the SPICE circuit netlist. By default, it generates a distinct external node for each die bump connected to off-chip structures and each pin connected to IO cells. An option is provided for a user to group bumps by region for accuracy and performance/capacity trade-off. The on-die interconnect model thus extracted enables a quick assessment of on-chip power and ground quality along with signal performance at every IO cell. Intuitive graphical representation of the electrical performance at each cell and query functions help designers easily verify each IO channel characteristics, quickly identify weak or problematic physical areas and perform what-if analysis to rapidly improve the design. Once the design meets the chip-level specification, the SI engineers can assemble the chip IO power, ground and signal interconnect model with other off-chip models through Cadence Model Connection Protocol (MCP) interface and perform the system-level IO SSO simulation. A typical die-to-die IO SSO simulation for a DDR memory interface, which includes power-aware IBIS (Input Output Buffer Information Specification) models for drivers and receivers, and distributed and coupled power/ground/signal models for chip, package and