DocumentCode
668912
Title
Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface
Author
Madden, Chris ; Hai Lan ; Zhuo Yan ; Kollipara, R. ; Jihong Ren
Author_Institution
Rambus Inc., Sunnyvale, CA, USA
fYear
2013
fDate
27-30 Oct. 2013
Firstpage
83
Lastpage
86
Abstract
The power integrity characterization of a high-capacity, compute-server memory system operating at 4.8Gbps-per-link is presented. The design robustness of the low-swing, single-ended signaling is verified as the system has excellent immunity to the noise from simultaneously switching outputs (SSO) and a low power-supply-induced jitter (PSIJ) at the primary chip-package resonance frequency.
Keywords
electronics packaging; flip-chip devices; memory architecture; multiprocessing systems; chip package resonance frequency; high capacity memory system; low power supply induced jitter; low swing single ended IO server memory interface; power integrity; simultaneously switching outputs; Clocks; Impedance; Jitter; Noise; Power supplies; Resonant frequency; Sensitivity; jitter; noise; power integrity;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on
Conference_Location
San Jose, CA
Print_ISBN
978-1-4799-0705-2
Type
conf
DOI
10.1109/EPEPS.2013.6703472
Filename
6703472
Link To Document