On-die supply-inducecd jitter behavioral modeling

This paper describes a simple, yet efficient supply-induced jitter modeling methodology for high-speed I/O circuits. The proposed model uses the average supply noise and a linear factor derived from Spice simulations to estimate the jitter for a circuit block. For circuits with bias voltages, the transfer function of the biasing network is included. The model is implemented in Simulink and closely correlated with Spice simulations. The modeling accuracy is further validated to be within ±15% of the silicon measurement for the period jitter of a ring oscillator. The jitter modeling technique is applied to multiple memory I/O designs and can be extended to other high-speed interface designs and their timing budgeting.