Title :
In-depth analysis of power noise coupling between core and periphery power rails
Author :
Guang Chen ; WernShin Choo ; Shishuang Sun ; Dan Oh
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
Core and periphery digital blocks often use the same voltage level. Due to the large current drawn by core, shielding periphery power from core power noise is highly desirable. This paper presents various separation schemes and compares pros and cons. Fundamental power noise coupling mechanisms between core and periphery powers are described in detail. Two major sources of power noise coupling are studied: inductive noise coupling and direct current draw through a common share point. Based on this analysis, we propose cost optimized board decoupling schemes.
Keywords :
CMOS integrated circuits; coupled circuits; field programmable gate arrays; integrated circuit interconnections; integrated circuit noise; printed circuit interconnections; printed circuits; core power noise; cost optimized board decoupling schemes; direct current; in depth analysis; inductive noise coupling; periphery digital blocks; periphery power rails; power noise coupling; Capacitors; Couplings; Ferrites; Impedance; Inductance; Noise; Rails; core and periphery power coupling; ferrite bead; power integrity; power separation; power transfer noise;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-0705-2
DOI :
10.1109/EPEPS.2013.6703501
