Analysis and verification of board power delivery network impact on DDR3L memory interface in ARM SoC application

Author

Tran, D.T. ; GaWon Kim ; Max Sunghwan Min ; Bautista, Harold ; Nian Zhou ; BaekKyu Choi ; Seungyong Cha ; Se-ho You

Author_Institution

Syst. LSI SoC Bay Area R&D (SBR), Samsung Semicond. Inc., San Jose, CA, USA

fYear

2013

fDate

27-30 Oct. 2013

Firstpage

215

Lastpage

218

Abstract

In this paper, a DDR3L simulation topology for ARM SoC application is presented and the impact of the board power delivery network (PDN) on a DDR3L memory interface is simulated and analyzed. The analysis of the DDR3L PDN of the package and board will be discussed in the frequency-domain while the DDR power noise and DDR3L data signals are analyzed in the time-domain. A timing jitter comparison of the measured and simulated eye-diagram is presented. Finally, the analysis verifies the importance of including the board PDN to accurately predict the performance of the DDR3L memory interface in the simulation and modeling environment.

Keywords

frequency-domain analysis; power electronics; system-on-chip; time-domain analysis; timing jitter; ARM SoC application; DDR power noise; DDR3L PDN; DDR3L data signals; DDR3L memory interface; DDR3L simulation topology; board power delivery network; frequency-domain; time-domain; timing jitter; Analytical models; Capacitors; Noise; Predictive models; System-on-chip; Timing jitter; Topology; ARM SoC; DDR3L; board PDN;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-0705-2

Type

conf

DOI

10.1109/EPEPS.2013.6703502

Filename

6703502