System-level optimization of on-chip communication using express links for throughput constrained MPSoCs

Application specific MPSoCs are often used for high end streaming applications, which impose stringent throughput constraints and raise the demand for application specific communication architectures. In this paper, we introduce a framework that selectively adds high bandwidth express links between communicating processors so that some traffic is directed via the express links rather than the baseline on-chip interconnect to improve MPSoC´s throughput. We present a novel heuristic, xLink, which exploits both processor latencies and on-chip traffic volume to efficiently prune the exponential design space and quickly reach the solution of minimal number of express links for a given throughput constraint. Our framework is oblivious to the baseline interconnect and therefore can be applied to different interconnects. We applied our framework to two different MPSoC interconnects: crossbar NoC and mesh NoC, using 9 benchmark applications. For crossbar NoC based MPSoC, xLink found the optimal solution in 24 out of 26 cases considered (with max error of 20%), while a traditional heuristic found the optimal solution in only 17 cases (with max error of 44%). For mesh NoC based MPSoC, xLink is better than traditional heuristic in 3 out of 9 cases considered with up to 11% saving in communication architecture area footprint. The xLink heuristic always took less than one hour, compared to several hours for the traditional heuristic and several days for an exhaustive algorithm. On average, xLink resulted in a runtime speedup of 7.5× for crossbar NoC topology, and 16.5× for mesh NoC topology, with respect to the traditional heuristic.