FPGA implementation of parallel unitary-rotation Jacobi EVD method based on Network-on-Chip

In this paper, a new design concept for accelerating parallel Jacobi method by using Network-on-Chip (NoC) is presented. The implementation of the Brent-Luk-EVD array is used as an example. In order to further study the tradeoff between the performance/complexity of EVD processors and the load/throughput of interconnects, a mesh structure NoC design based Jacobi EVD array with the simplified μ-CORDIC processor PE has be implemented on FPGA. The hardware experimental results show that using a NoC architecture makes it able to deal with large-scale size EVD problem and reduce the computation time.