DocumentCode :
669775
Title :
Color-space image compression with hardware Self-organizing map
Author :
Terahara, Naoki ; Oba, Y. ; Hikawa, Hiroomi
Author_Institution :
Grad. Sch. of Sci. & Eng., Kansai Univ., Suita, Japan
fYear :
2013
fDate :
12-15 Nov. 2013
Firstpage :
11
Lastpage :
16
Abstract :
This paper discusses the use of Self-organizing map (SOM) for color-space image compression. Two types of compressions, i.e., color and space compressions, are carried out by SOM. The feasibility of the proposed compression method is verified by computer simulation. By applying both color and space compression, higher compression is achieved. In addition, the proposed compression system is implemented in hardware using a hardware SOM. The system is designed by using VHDL, and operation of the system is verified by FPGA implementation. Experimental result shows that the maximum clock frequency of this system is 26 MHz, and a single image is compressed with 25.2 ms, which yields 39.7 fps.
Keywords :
data compression; field programmable gate arrays; image coding; image colour analysis; self-organising feature maps; FPGA implementation; VHDL; computer simulation; frequency 26 MHz; hardware SOM; hardware self-organizing map; maximum clock frequency; time 25.2 ms; time 39.7 fs; Color; Hardware; Image coding; Image color analysis; Neurons; Training; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2013 International Symposium on
Conference_Location :
Naha
Print_ISBN :
978-1-4673-6360-0
Type :
conf
DOI :
10.1109/ISPACS.2013.6704514
Filename :
6704514
Link To Document :
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