DocumentCode :
669803
Title :
Performance-power analysis of H.265/HEVC and H.264/AVC running on multicore cache systems
Author :
Asaduzzaman, Abu ; Suryanarayana, Vidya R. ; Rahman, Mosaddequr
Author_Institution :
Dept. of Elec. Eng. & Comput. Sci., Wichita State Univ., Wichita, KS, USA
fYear :
2013
fDate :
12-15 Nov. 2013
Firstpage :
174
Lastpage :
179
Abstract :
The leading problem of adopting caches into multicore computing systems is twofold: cache worsens execution time unpredictability (that challenges supporting real-time multimedia applications) and cache is power hungry (that challenges energy constraints). Recently published articles suggest that using cache locking improves timing predictability. However, increased cache activities due to aggressive cache locking make the system consume more energy and become less efficient. In this paper, we investigate the impact of multicore cache parameters and cache locking on performance and power consumption for real-time multimedia applications. We consider an Intel Xeon-like multicore architecture with two-level cache memory hierarchy and use two popular multimedia applications: recently introduced H.265/HEVC (for improved video quality and data compression ratio) and H.264/AVC (the network friendly video coding standard). Experimental results suggest that cache optimization has potential to improve multicore performance by decreasing cache miss rate down to 36% and save power consumption up to 33%. It is observed that H.265/HEVC has significant performance advantage on multicore system over H.264/AVC for smaller cache memories.
Keywords :
cache storage; power consumption; telecommunication standards; video coding; H.264/AVC running; H.265/HEVC; Intel Xeon-like multicore architecture; cache memories; data compression ratio; multicore cache systems; multicore computing systems; multicore system; power consumption; two-level cache memory; video coding standard; video quality; Decoding; Multicore processing; Multimedia communication; Power demand; Streaming media; Transform coding; Video coding; Cache memory hierarchy; cache optimization; multicore architecture; multimedia applications; performance and power analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2013 International Symposium on
Conference_Location :
Naha
Print_ISBN :
978-1-4673-6360-0
Type :
conf
DOI :
10.1109/ISPACS.2013.6704542
Filename :
6704542
Link To Document :
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