DocumentCode
669835
Title
A new winner-take-all neural network using DPLL and phase modulated signal
Author
Azuma, Masaki ; Hikawa, Hiroomi
Author_Institution
Grad. Sch. of Sci. & Eng., Kansai Univ., Suita, Japan
fYear
2013
fDate
12-15 Nov. 2013
Firstpage
345
Lastpage
350
Abstract
Due to superior learning ability, neural network is widely used in various fields. This paper proposes a hardware winner-take-all neural network (WTANN) which has a new winner-take-all (WTA) circuit with phase-modulated pulse signal and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. In hardwareWTANN, the proposed winner search method is implemented with simple circuit. The proposed WTANN architecture is described by VHDL and its feasibility is verified by simulation. Then its circuit size and speed are evaluated by applying the VHDL description to logic synthesis tool. Results show that the proposed WTANN has valid learning characteristics.
Keywords
digital phase locked loops; logic design; neural nets; phase modulation; search problems; DPLL; VHDL description; WTANN architecture; circuit size; computing element; digital phase-locked loops; learning characteristics; logic synthesis tool; phase-modulated pulse signal; rectangular signals; winner search method; winner-take-all circuit; winner-take-all neural network; Biological neural networks; Integrated circuit modeling; Iris recognition; Neurons; Radiation detectors; Timing; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communications Systems (ISPACS), 2013 International Symposium on
Conference_Location
Naha
Print_ISBN
978-1-4673-6360-0
Type
conf
DOI
10.1109/ISPACS.2013.6704574
Filename
6704574
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