Title :
FPGA based architecture for real-time SAR processing with integrated motion compensation
Author :
Pfitzner, M. ; Cholewa, F. ; Pirsch, P. ; Blume, Holger
Author_Institution :
Inst. of Microelectron. Syst. (IMS), Leibniz Univ. Hannover, Hannover, Germany
Abstract :
In this paper, an FPGA based hardware architecture for airborne real-time SAR image generation with integrated first-order motion compensation (MoCom) is presented. By sharing the same FPGA resources for image generation and correction of highly squinted flight path deviations, only marginal overhead in terms of additional hardware resources is required when compared to an implementation without resource sharing. The proposed architecture has been implemented and evaluated on a Xilinx Virtex-6 ML-605 Evaluation Kit for different flight path deviation and squint parameter settings. An average throughput rate of 25 MSamples/s (32-bit/sample) is reached while the FPGA resource allocation does not exceed 50% of the LUT slices (logic), 45% of the BRAM36 (memory) and less than 8% of the DSP48 slices.
Keywords :
field programmable gate arrays; geophysical image processing; motion compensation; radar imaging; remote sensing by radar; BRAM36; DSP48 slices; FPGA based architecture; FPGA based hardware architecture; FPGA resources; LUT slices; Xilinx Virtex-6 ML-605 Evaluation Kit; airborne real time SAR image generation; highly squinted flight path deviations; image correction; integrated first order motion compensation; integrated motion compensation; real time SAR processing; Azimuth; Computer architecture; Field programmable gate arrays; Hardware; Signal processing; Signal processing algorithms; Synthetic aperture radar;
Conference_Titel :
Synthetic Aperture Radar (APSAR), 2013 Asia-Pacific Conference on
Conference_Location :
Tsukuba