Title :
STT-MRAM and NV-Logic for low power systems
Author_Institution :
Grad. Sch. of Eng., Tohoku Univ., Sendai, Japan
Abstract :
Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.
Keywords :
MOSFET; MRAM devices; large scale integration; leakage currents; logic circuits; low-power electronics; power consumption; LSI; MOSFET; NV-logic; STT-MRAM; device scaling; leakage current; low power systems; memory capacity; operation speed; power consumption; semiconductor memories; Junctions; Magnetic tunneling; Magnetoelectronics; Memory management; Nonvolatile memory; Random access memory; Very large scale integration;
Conference_Titel :
Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on
Conference_Location :
Berkeley, CA
DOI :
10.1109/E3S.2013.6705864
