DocumentCode
670665
Title
STT-MRAM and NV-Logic for low power systems
Author
Endoh, Tetsuo
Author_Institution
Grad. Sch. of Eng., Tohoku Univ., Sendai, Japan
fYear
2013
fDate
28-29 Oct. 2013
Firstpage
1
Lastpage
2
Abstract
Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.
Keywords
MOSFET; MRAM devices; large scale integration; leakage currents; logic circuits; low-power electronics; power consumption; LSI; MOSFET; NV-logic; STT-MRAM; device scaling; leakage current; low power systems; memory capacity; operation speed; power consumption; semiconductor memories; Junctions; Magnetic tunneling; Magnetoelectronics; Memory management; Nonvolatile memory; Random access memory; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on
Conference_Location
Berkeley, CA
Type
conf
DOI
10.1109/E3S.2013.6705864
Filename
6705864
Link To Document