Electrostatic design of vertical tunneling field-effect transistors

Tunneling field-effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of the subthreshold swing for conventional devices enabling lower power electronics. However, as shown in the TFET review by Seabaugh and Zhang [1], experimental subthreshold characteristics have not achieved the steepness of theoretical predictions. Possible explanations for the non-abrupt turn-on of experimental devices include long band-tails (exacerbated by doping) that extend into the semiconductor band gap, mid-gap and interface trap-states, inhomogeneity of the semiconductor composition, strain and/or thickness, and non-optimal electrostatic design of the transistor structure. This paper focuses on improving the electrostatic design of vertical tunneling structures (where tunneling occurs vertically toward the gate), in order to better experimental turn-on characteristics.