Title :
Threshold voltage optimization in a 22nm High-k/Salicide PMOS device
Author :
Maheran, A. H. Afifah ; Menon, P. Susthitha ; Ahmad, Ishtiaq ; Yusoff, Z.
Author_Institution :
Inst. of Microeng. & Nanoelectronic (IMEN), Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia
Abstract :
In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi´s experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi´s nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of Vth. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.
Keywords :
MOSFET; Taguchi methods; design of experiments; electrical resistivity; elemental semiconductors; high-k dielectric thin films; permittivity; semiconductor device models; semiconductor device noise; silicon; titanium compounds; ANOM; ANOVA; ATHENA simulation; ATLAS simulation; ITRS 2011; L9 Taguchi experimental design; PMOS device; TiO2-Si; analysis of the mean; analysis of variance; electrical characterization; gate electrode resistance; gate length; high-k dielectric layer; noise parameters; permittivity material; process parameters; self-aligned silicide layer; signal-to-noise ratio analysis; size 22 nm; threshold voltage optimization; titanium dioxide; virtual fabrication device; Annealing; High K dielectric materials; Logic gates; MOS devices; Noise; Silicides; Threshold voltage; 22 nm gate length PMOS; Taguchi Method; high-k/SALICIDE; threshold voltage;
Conference_Titel :
Micro and Nanoelectronics (RSM), 2013 IEEE Regional Symposium on
Conference_Location :
Langkawi
Print_ISBN :
978-1-4799-1181-3
DOI :
10.1109/RSM.2013.6706489